An integrated circuit containing field oxide made by a shallow trench isolation (STI) process includes an oxide planarization step using a chemical mechanical polish (CMP) process. The CMP process overpolishes large areas of low active area density, such as resistor areas, producing thin field oxide in these areas with unpredictable thickness profiles. Well resistors made under overpolished field oxide have low, erratic resistance due to more implanted dopants passing through the thin field oxide. Resistors of polycrystalline silicon, referred to as polysilicon, on overpolished field oxide, in which the polysilicon has been planarized with another CMP process, tend to have high, erratic, thicknesses leading to low, variable resistance and undesired variation in temperature dependence of the resistance.